The present disclosure relates to semiconductor memory devices, and more particularly, to techniques of controlling the potential of a bit line in a memory circuit.
Conventionally, there is a known technique of stepping down the potential of a bit line by driving an N-channel MOS (NMOS) transistor connected to the bit line using a pulse in order to improve the static noise margin (SNM) of a memory cell in a static random access memory (SRAM). Note that data is read out using a sense amplifier which detects a minute potential difference between a pair of bit lines (see M. Khellah et al., “Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65 nm CMOS Designs,” 2006 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 12-13).
There is also a known technique of controlling the potential level of a signal line in a decoder circuit to drive a word line in a semiconductor memory device (see Japanese Patent Publication No. 2007-164922).